Title :
Power LDMOS with novel STI profile for improved Rsp, BVdss, and reliability
Author :
Haynie, S. ; Gabrys, A. ; Kwon, T. ; Allard, P. ; Strout, J. ; Strachan, A.
Author_Institution :
Analog Process Integration, Nat. Semicond. Corp, Santa Clara, CA, USA
Abstract :
The profile of shallow trench isolation (STI) is designed to improve LDMOS specific on-resistance (Rsp), BVDSS, safe operating area (SOA), and hot carrier lifetimes (HCL) in an integrated BiCMOS power technology. Silicon etch, liner oxidation and CMP processes are tuned to improve the tradeoffs in a power technology showing significant improvement to both p-channel and n-channel Rsp compared to devices fabricated with the STI profile inherited from the original submicron CMOS platform. Extensive TCAD and experiments were carried out to gain insight into the physical mechanisms and further improve device performance after STI process optimization. The final process and device structures yield SOAs that are limited only by thermal constraints up to rated voltages.
Keywords :
BiCMOS integrated circuits; carrier lifetime; chemical mechanical polishing; isolation technology; oxidation; power MOSFET; semiconductor device reliability; technology CAD (electronics); BiCMOS power technology; TCAD; chemical mechanical polishing; hot carrier lifetime; liner oxidation; power LDMOS; safe operating area; shallow trench isolation; specific on-resistance; BiCMOS integrated circuits; CMOS process; CMOS technology; Etching; Hot carriers; Isolation technology; Oxidation; Performance gain; Semiconductor optical amplifiers; Silicon;
Conference_Titel :
Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
Conference_Location :
Hiroshima
Print_ISBN :
978-1-4244-7718-0
Electronic_ISBN :
1943-653X
