DocumentCode
525895
Title
A 200V Partial SOI 0.18µm CMOS technology
Author
Hölke, Alexander ; Pal, Deb Kumar ; Hao, Yang ; Yaw, Kee Kia ; Kho, Elizabeth ; Kittler, Gabriel ; Kuniss, Uta ; Gessner, Jörg
Author_Institution
Process Dev., X-Fab Sarawak Sdn. Bhd., Kuching, Malaysia
fYear
2010
fDate
6-10 June 2010
Firstpage
257
Lastpage
260
Abstract
A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and area-efficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a wide-range breakdown voltage-scaling capability.
Keywords
CMOS integrated circuits; isolation technology; silicon-on-insulator; CMOS technology; HVMOS; dielectric isolation; integrated technology; lateral super junctions devices; partial SOI; size 0.18 mum; wide-range breakdown voltage-scaling capability; Breakdown voltage; CMOS process; CMOS technology; Dielectric devices; Dielectric substrates; Diodes; Foundries; Power semiconductor devices; Semiconductor device doping; Ultrasonic imaging;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
Conference_Location
Hiroshima
ISSN
1943-653X
Print_ISBN
978-1-4244-7718-0
Electronic_ISBN
1943-653X
Type
conf
Filename
5543985
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