DocumentCode :
526263
Title :
Design and implementation of a highly configurable low power robust signal processor for portable ground based “multiple scan rate” surveillance radar
Author :
Jena, Paramananda ; Chandrakanth, V. ; Tripathi, Bhishm ; Kuloor, Ramachandra ; Nasir, Wasim
Author_Institution :
Electron. & Radar Dev. Establ., Bangalore, India
fYear :
2010
fDate :
16-18 June 2010
Firstpage :
1
Lastpage :
4
Abstract :
FPGA based realization of a highly configurable low-power robust signal processor for a portable ground-based multiple scan ratesurveillance radar is presented. Portability feature of the radar demands a compact radar system which should be able to detect low flying aerial targets against clutter/interference background. All requirements could be met in a FPGA-based design of a multi-channel signal processor to cater for low peak power large bandwidth waveforms, separate processing for special targets and an embedded softcore processor. Reliable self-test mechanisms – external as well as internal have been built into the signal processor for functional verification of entire radar system.
Keywords :
Built-in self-test; Clutter; Computer architecture; Doppler effect; Field programmable gate arrays; Filter bank; Radar; BMWD; CFAR; Digital Pulse Compression; EMC; FPGA; LVDS; MFS; NIOS™soft core processor; PRT; Surveillance Radar; Variable Point FFT;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radar Symposium (IRS), 2010 11th International
Conference_Location :
Vilnius, Lithuania
ISSN :
2155-5754
Print_ISBN :
978-1-4244-5613-0
Type :
conf
Filename :
5547503
Link To Document :
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