Power analysis of parallel CA-CFAR FPGA design

We provide a power analysis of a parallel implementation of the Cell Average Constant False Alarm Rate (CA-CFAR) algorithm in reconfigurable hardware, originally proposed by the authors. The design is based on a parallel processing scheme employing extensive data reuse and synchronized sliding windows over the input data sequence. A scalable parallel structure is designed and mapped on Xilinx Virtex II Pro and Altera Stratix I technology. Synthesis and post place and route results from the Xilinx ISE and Quartus II toolset suggest a linear speedup and resource utilization. More specifically, a single CFAR implementation utilizes 1.4% of the VIRTEX II Pro XC2VP30 chip and 2% for Altera EP1S25F780C5 chip, providing a throughput of 974 Mbps. The power consumption of the design is evaluated per technology. The maximum allowed frequencies are determined and compared, as well.