Title :
A DFTR router architecture for 3D Network on Chip
Author :
Zhang, Yuyang ; Hu, Jianao
Author_Institution :
Nat. Key Lab. of Sci. & Technol. on Commun., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
In this paper, we proposed a dual flit transmission rate (DFTR) router architecture according to the property of short distance for the inter-wafer links for 3D Network on Chip (NoC). The equivalent bandwidth of the inter-wafer links can be N times wider than that of the intra-wafer links, since flit transmission rate in vertical direction can be N times fast than that in the horizon direction. Thus, the flits, which transfer through the DFTR router in the vertical direction, only take the 1/N time that is needed in the horizon direction. According to the performance simulation results, packet latency reduced about 20% and 40%, throughput improved about 7% and 30%, for 4×4×4 3D and 2 × 2 × 8 3D mesh network respectively, compared with the router which the vertical flit transmission rate is same with the rate in plane, when N=4.
Keywords :
network routing; network-on-chip; three-dimensional integrated circuits; 3D mesh network; 3D network on chip; DFTR router; dual flit transmission rate; inter-wafer links; packet latency; Adaptation model; Routing; Switches; Topology; Tornadoes; Variable speed drives; 3D NoC; performance evaluation; router architecture; virtual output queue; wormhole switch;
Conference_Titel :
Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-5537-9
DOI :
10.1109/ICCSIT.2010.5563572
