• DocumentCode
    52641
  • Title

    Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

  • Author

    Keheng Huang ; Yu Hu ; Xiaowei Li

  • Author_Institution
    State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
  • Volume
    22
  • Issue
    2
  • fYear
    2014
  • fDate
    Feb. 2014
  • Firstpage
    256
  • Lastpage
    269
  • Abstract
    As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become increasingly vulnerable to soft errors. Existing reliability-oriented placement and routing approaches primarily focus on reducing the fault occurrence probability (node error rate) of soft errors. However, our analysis shows that, besides the fault occurrence probability, the propagation probability (error propagation probability) plays an important role and should be taken into consideration. In this paper, we first propose a cube-based analysis algorithm to efficiently and accurately estimate the error propagation probability. Based on such a model, we propose a novel reliability-oriented placement and routing algorithm that combines both the fault occurrence probability and the error propagation probability together to enhance system-level robustness against soft errors. Experimental results show that, compared with the baseline versatile place and route technique, the proposed scheme can reduce the failure rate by 20.73%, and increase the mean time between failures by 39.44%.
  • Keywords
    SRAM chips; field programmable gate arrays; integrated circuit reliability; integrated logic circuits; nanoelectronics; network routing; probability; radiation hardening (electronics); SRAM-based FPGAs; cube-based analysis algorithm; error propagation probability; fault occurrence probability; nanometer scale; node error rate; reliability-oriented placement; routing algorithm; soft error mitigation; system-level robustness; Circuit faults; Field programmable gate arrays; Integrated circuit reliability; Measurement; Routing; Wires; Cube-based analysis; failure rate; field-programmable gate arrays (FPGAs); mean time between failures (MTBFs); placement and routing; soft error mitigation;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2013.2239318
  • Filename
    6459610