Title :
FPGA implementation of Gaussian-distributed pseudo-random number generator
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
Abstract :
This paper proposes a simple but practical Gaussian-distributed pseudo-random number generator. The features of this generator include a compact architecture based on a decimator connected linear feedback shift register, Gaussian-distributed N-bit random number output, long period of a random number sequence, and good statistical properties.
Keywords :
Gaussian distribution; feedback; field programmable gate arrays; random number generation; random sequences; shift registers; FPGA implementation; Gaussian distributed pseudorandom number generator; compact architecture; decimator connected linear feedback shift register; random number sequence; Adders; Clocks; Radiation detectors; FPGA; Gaussian distribution; decimator; random number generator;
Conference_Titel :
Digital Content, Multimedia Technology and its Applications (IDC), 2010 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-7607-7
Electronic_ISBN :
978-8-9886-7827-5
