A novel high frequency pseudo noise correlator hardware design for cable fault diagnoses

A novel modification of a cross-correlation algorithm has been designed and implemented as digital hardware process. The algorithm was written in Verilog and tested running on FPGA hardware at 100 MHz. The algorithm presented has a modular architecture that is fully scalable and can be used to correlate a large number of different length pseudo random binary sequences (PRBS). A real-world interface (digital to analog and analog to digital converter) is added to the FPGA implementation to validate the algorithm in the field of cable testing and fault finding. The algorithm was functionality validated through coaxial cable testing and benchmarked for accuracy against known test results.