Impact of dual placement on WDDL design security in Mesh-based and Tree-based FPGAs

The Wave Dynamic Differential Logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail signals in WDDL design. We describe placement techniques suitable for Tree-based and Mesh-based FPGAs, and quantify the gain that they confer. Experimental results show that the placement affects significantly the dual-rail unbalance. In fact, the average delay unbalance in WDDL DES netlist was reduced by 72% in the Tree FPGA and by 82% in the Mesh FPGA using adapted placement techniques.