Power-gating: More than leakage savings

While CMOS technology keeps running towards the physical limit of “nanometer” lengths, many critical design issues have already appeared in today´s technologies (65nm and 45nm). Among them, Power and Reliability are the most insidious, because they affect energy efficiency and life-time of digital systems. In this work we establish an important link between these two metrics. More specifically, we show how the most widely adopted leakage-reduction technique, that is power-gating, can go beyond its specific goal (i.e., saving leakage) by providing, per se, an effective solution to mitigate NBTI-induced aging. Based on this important property, we first present an automated methodology that allows a push-button estimation of the aging effects induced by NBTI on logic circuits (in terms of delay degradation) and SRAM memory cells (in terms of Static Noise Margin (SNM) reduction). Second, using an industrial 45nm technology, we quantify the actual capability of power-gating to further reduce the aging of CMOS devices and extend the lifetime of digital circuits.