Implementation of realtime pipeline-folding 64-tap filters on FPGA

To transfer functionalities from software to dedicated hardware is necessary when the performance of the available DSP processor can not achieve the required constraints. The hardware implementations of pipeline-folding 64-Tap filter modules used in a heavy ion accelerator for real-time digital signal processing are described in this paper. Pipeline-folding mechanism is applied to the hardware designs in order to achieve the time and area constraints at 1.5 MHz and 50 % of the available FPGA resources. Based on this mechanism, six filter architectures are proposed and realized on FPGA Xilinx VitexII 2V2000. The synthesized results show the possibility to include two filter modules which are used to compute the streaming 16-bit input generated from CORDIC module into the specific system in parallel. Moreover, the estimated power consumption of these architectures are reported. The hardware operations and the performance of these architectures are compared with the straight pipeline filter and the traditional filter where introduced architectures can achieve higher performance and lower resource usages.