TDM switch-based crossbar architecture for SoC on FPGA

The communication mechanisms employed on system-on-chips(SoCs) are an important contribution to their overall performance. To date, bus-based paradigm is applied in many areas of real-time applications of SoCs realizing on FPGA due to its flexibility and simplification in designing tool. Although offering the module-increasing flexibility, its bandwidth and scalability still become problem. To alleviate these problems, switch-based paradigm has been introduced to improve the above two factors. In addition, its changeable communication-pattern characteristic depending on various applications at run-time is advantageous. Thus, the possibility of multiple applications running on single platform can be achieved. Nevertheless, many-to-one (gathering) functionality based on the switch-based paradigm has disadvantage at output delay. In this paper, Time Division Multiplexer (TDM) mechanism is introduced to solve the delay problem. Moreover, 6x6 TDM switch-based crossbar architecture is implemented and verified on Xilinx FPGA Virtex2P XC2VP30. Verifying its performance with 256-word samples at 100 MHz and measuring the gathered output by logic analyzer, the maximum bandwidth is 741.32 Mbit/sec in many-to-one, and 533 Mbit/sec in one-to-many. Flip-Flop and LUTs are 3.33% and 16.05% of the target FPGA; likewise, estimation frequency respond is 113.854 MHz obtained from the Xilinx ISE tool.