DocumentCode
527957
Title
An 8-bit 440-MS/s pipelined Analog-to-Digital Converter in 0.13-µm CMOS
Author
Nieminen, Tero ; Halonen, Kari
Author_Institution
Dept. of Micro- & Nanosci., Aalto Univ., Aalto, Finland
fYear
2010
fDate
18-21 July 2010
Firstpage
1
Lastpage
4
Abstract
In this paper, an 8-bit, 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. Simulated effective number of bits (ENOB) of the ADC is 7.09 with the most critical parasitics included and 162-MHz full-scale input, while the current drawn from 1.2V supply is 83mA.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; operational amplifiers; CMOS process; current 83 mA; double sampling; effective number of bits; frequency 162 MHz; operational amplifier settling time requirements; pipelined analog-to-digital converter; redundant sign digit correction; size 0.13 mum; voltage 1.2 V; CMOS integrated circuits; Capacitors; Clocks; Converters; Integrated circuit modeling; Pipelines; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Ph.D. Research in Microelectronics and Electronics (PRIME), 2010 Conference on
Conference_Location
Berlin
Print_ISBN
978-1-4244-7905-4
Type
conf
Filename
5587161
Link To Document