Hardware reduction in higher order MASH Digital Delta-Sigma Modulators via error masking

An error masking technique has been developed which allows the hardware complexity of Multi stAge noise SHaping (MASH) Digital Delta-Sigma Modulators (DDSMs) to be reduced without sacrificing performance. This technique has already been applied to the conventional MASH 1-1-1 DDSM and it has been shown that 20% hardware savings can be achieved compared to the conventional design. In this work, we use the error masking strategy to develop a design methodology for higher order reduced complexity (RC) MASH DDSMs. We present in detail the design methodology for an RC MASH 1-1-1-1 DDSM, and provide the necessary design equations to implement an RC MASH 1-1-1-1-1 DDSM, without elaborating on the detail. Simulation results are presented which confirm the theoretical predictions.