An ultra low-power CMOS frequency synthesizer for low data-rate sub-GHz applications

An ultra low-power frequency synthesizer for sub-GHz applications was designed and implemented in a 90-nm CMOS technology. Based on an integer-N phase-locked loop architecture, the frequency synthesizer covers the 0.3-0.95 GHz band almost continuously with 150-kHz channel steps. Multi-band operation is achieved thanks to a wideband low-power LC VCO, which makes use of shunt-connected switched-coupled inductors. Power consumption has been minimized by adopting true single-phase clocked logic cells for the first stages of the programmable divider. The frequency synthesizer achieves a phase noise of -96 dBc/Hz at 150-kHz offset frequency. The measured settling time is around 350 μS and the reference spurs are lower than -52 dBc. The circuit power consumption is only 1.8 mW from a 1.2-V supply.