DocumentCode :
528626
Title :
Dynamic reconfiguration of threads in real-time system working on precision time regime
Author :
Pulka, Andrzej ; Milik, Adam
Author_Institution :
Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
fYear :
2010
fDate :
7-10 Sept. 2010
Firstpage :
339
Lastpage :
342
Abstract :
The paper concerns design of real time systems that meet precision time (PRET) requirements. A new, original architecture of the multithread embedded system with programmable interleaved pipelining is introduced. Main components are described with special attention devoted to the interleave controller. This element of the system is responsible for controlling of the order of threads loaded into the processor´s pipeline. The idea of shadow deadline processing arbiter responsible for dynamic reconfiguration of performed threads (tasks) is given. Results of the implementation and simulation of different arbitration schemes are discussed. Conclusions emphasizing the flexibility and advantages of the proposed solution summarize the paper.
Keywords :
embedded systems; interleaved storage; multi-threading; pipeline processing; dynamic reconfiguration; multithread embedded system; precision time regime; processor pipeline; programmable interleaved pipelining; real time system; shadow deadline processing arbiter; Computer architecture; Instruction sets; Pipeline processing; Pipelines; Process control; Registers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals and Electronic Systems (ICSES), 2010 International Conference on
Conference_Location :
Gliwice
Print_ISBN :
978-1-4244-5307-8
Electronic_ISBN :
978-83-9047-4-2
Type :
conf
Filename :
5595179
Link To Document :
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