High speed CAVLC encoder suitable for field programmable platforms

In this paper a new Context-Adaptive Variable-Length Coding encoder is proposed particularly aimed to be implemented with Field Programmable Logics. The design employs redundant circuitry to implement priority cascading logics which allows to highly improve its degree of parallelism, while the area cost related to the unavoidable replication of logic blocks has been balanced by means of arithmetic manipulations capable to eliminate some of the most area demanding tables of variable-length codewords. The proposed design is capable to process 1080p@30 HDTV video streams coded in YCbCr 4:2:0, when it is implemented with a low-cost, low-speed FPGA.