Statistical power analysis for nanoscale CMOS

With the scaling down of CMOS technology, process variations are becoming significant. Power consumption is a major constraint on IC yield. However, there has been little research on statistical power analysis compared with that on timing analysis. Here, both the static and dynamic power are considered. We characterize a cell library containing mean power. A standard deviation power library is extracted from Monte Carlo simulations. Then, the mean and variance of the power are derived. The proposed technique is validated on benchmark circuits at 35 nm. We compare the results with SPICE simulations and show that the difference is acceptable.