• DocumentCode
    528795
  • Title

    A three-step power-gating turn-on technique for controlling ground bounce noise

  • Author

    Singh, Rahul ; Kim, AhReum ; Kim, SoYoung ; Kim, Suhwan

  • Author_Institution
    Electrical Engineering, Seoul National University, Seoul, Korea
  • fYear
    2010
  • fDate
    18-20 Aug. 2010
  • Firstpage
    171
  • Lastpage
    176
  • Abstract
    To suppress the ground bounce noise with a minimal wake-up time penalty, a three-step turn-on strategy and its corresponding power-gating structure are proposed. During the circuit´s meta-stable region of operation, specifically, the amount of current flowing through the sleep transistors is precisely controlled while the virtual or circuit power supply is quickly boosted when the internal nodes of the circuit are stable. In 65 nm CMOS technology, simulation results demonstrate that our technique reduces the peak amplitude of the ground bouncing noise by up to 94% as compared to the conventional abrupt turn-on technique.
  • Keywords
    Capacitors; Noise; Power supplies; Rails; Switches; Switching circuits; Transistors; Power-gating; ground bounce; inductive noise; mode transition; system-on-a-chip (SOC) design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on
  • Conference_Location
    Austin, TX, USA
  • Print_ISBN
    978-1-4244-8588-8
  • Type

    conf

  • Filename
    5599017