Title :
Frame and arithmetic pipelining for a radix-4 FFT streamed core
Author :
Rodríguez, J. Agustín ; Julián, Pedro M. ; Andreou, Andreas G.
Author_Institution :
Dept. de Ing. Electr. y Computadoras, Univ. Nac. del Sur, Bahía Blanca, Argentina
Abstract :
This work presents the architecture of a pipelined 512 point radix 4-2 Fast Fourier Transform (FFT) core. Two pipelining dimensions were specified. The frame pipeline manages the data frames (input, current and output) and ensures a continuous-flow maintaining input/output transactions and the FFT evaluation without any stalls. The arithmetic pipeline was optimized by an iterative logic synthesis study down with Design Compiler to push the clock frequency to 1 GHz. This under-development FFT core was implemented with Hardware Description Language (HDL) and logically and physically synthesized with standard Electronic Design Automation (EDA) tools for a 130 nm process.
Keywords :
digital arithmetic; fast Fourier transforms; integrated circuit design; microprocessor chips; reconfigurable architectures; EDA tools; HDL; VLSI; arithmetic pipelining; clock frequency; design compiler; fast Fourier transform; frame pipelining; frequency 1 GHz; hardware description language; iterative logic synthesis; microprocessor architecture; radix-4 FFT streamed core; size 130 nm; standard electronic design automation; Algorithm design and analysis; Clocks; Computer architecture; Discrete Fourier transforms; Pipeline processing; Registers; Signal processing algorithms; Fast Fourier Transform; Logic Synthesis; Microprocessor Architecture; VLSI;
Conference_Titel :
Argentine School of Micro-Nanoelectronics Technology and Applications (EAMTA), 2010
Conference_Location :
Montevideo
Print_ISBN :
978-1-4244-6747-1
Electronic_ISBN :
978-987-1620-14-2