Frame and arithmetic pipelining for a radix-4 FFT streamed core

This work presents the architecture of a pipelined 512 point radix 4-2 Fast Fourier Transform (FFT) core. Two pipelining dimensions were specified. The frame pipeline manages the data frames (input, current and output) and ensures a continuous-flow maintaining input/output transactions and the FFT evaluation without any stalls. The arithmetic pipeline was optimized by an iterative logic synthesis study down with Design Compiler to push the clock frequency to 1 GHz. This under-development FFT core was implemented with Hardware Description Language (HDL) and logically and physically synthesized with standard Electronic Design Automation (EDA) tools for a 130 nm process.