DocumentCode :
530188
Title :
A 10-Gb/s CMOS differential transimpedance amplifier for parallel optical receiver
Author :
Chen, Lili ; Li, Zhiqun ; Wang, Zhigong ; Li, Wei ; Zhang, Li
Author_Institution :
Inst. of RF - & OE - Ics, Southeast Univ., Nanjing, China
Volume :
1
fYear :
2010
fDate :
17-20 Sept. 2010
Firstpage :
1
Lastpage :
4
Abstract :
A 10-Gb/s transimpedance amplifier (TIA) for the parallel optical receiver module is realized in 0.18-μm CMOS technology. The proposed TIA employs a regulated cascode (RGC) input structure and adopts active inductor peaking and feedback techniques to enhance the bandwidth. Besides, a noise optimization is processed. The TIA provides a conversion gain of 50 dBΩ and 3-dB bandwith of 7 GHz. The measured sensitivity is about 35 μA at a bit error rate of 10-12 with a 231-1 pseudorandom test pattern for 10 Gb/s operation. Under a 1.8-V supply voltage, the differential TIA consumes 29.2 mW, counting an output buffer. The core chip area is 144×160 μm2 excluding the output buffer and testing pads.
Keywords :
CMOS integrated circuits; differential amplifiers; feedback amplifiers; inductors; low-power electronics; operational amplifiers; optical receivers; CMOS differential transimpedance amplifier; active inductor peaking technique; bandwidth 7 GHz; bit rate 10 Gbit/s; current 35 muA; feedback technique; gain 3 dB; gain 50 dB; noise optimization; parallel optical receiver; power 29.2 mW; regulated cascode input structure; size 0.18 mum; voltage 1.8 V; Arrays; Bandwidth; CMOS integrated circuits; Current measurement; Noise; Optical fiber amplifiers; Optical receivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals Systems and Electronics (ISSSE), 2010 International Symposium on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-6352-7
Type :
conf
DOI :
10.1109/ISSSE.2010.5607130
Filename :
5607130
Link To Document :
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