Graded channel concept for improving RF noise of an industrial 0.15 µm SOI CMOS technology

Author

Emam, M. ; Sakalas, P. ; Kumar, A. ; Ida, J. ; Vanhoenacker-Janvier, D. ; Raskin, J.P. ; Danneville, F.

Author_Institution

Electr. Eng. Dept., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium

fYear

2010

fDate

27-28 Sept. 2010

Firstpage

170

Lastpage

173

Abstract

In this work, the graded channel concept has been introduced into a fully-depleted 0.15 μm SOI CMOS technology through a commercial industrial fabrication process in order to improve the RF noise performance of deep submicron scale devices. The benefits of using a graded channel transistor are explicit. An improved minimum noise figure is achieved while relaxing the minimum feature size to, at least, one technology node backward. The standard CMOS process is slightly changed by introducing one extra mask only to the fabrication process.

Keywords

CMOS integrated circuits; MOSFET; masks; semiconductor device noise; silicon-on-insulator; CMOS process; RF noise performance; commercial industrial fabrication process; deep submicron scale devices; fully-depleted SOI CMOS technology; graded channel concept; graded channel transistor; industrial SOI CMOS technology; mask; minimum feature size; minimum noise figure; size 0.15 mum; technology node backward; Frequency measurement; Logic gates; MOSFETs; Noise; Performance evaluation; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Integrated Circuits Conference (EuMIC), 2010 European

Conference_Location

Paris

Print_ISBN

978-1-4244-7231-4

Type

conf

Filename

5613677