Area-efficient integrated antennas for inter-chip communication

This work discusses the design and the experimental verification of integrated on-chip antennas. The antennas use the CMOS ground supply metallisation layer as radiating elements, therefore the additional chip area required by the antenna is minimised. This has been achieved by dividing the top CMOS metallisation layer into patches and feeding the RF signals across the slots. If the carrier frequency for the wireless chip-to-chip link is chosen high enough, such antennas operate as slot antennas. The simulation results have been verified by an experimental prototype of the proposed structures.