2Gbps CMOS amplitude-shift-keying demodulator with input sensitivity of −33dBm

High-speed pulse communication is attaching increasing attention. The high-speed amplitude-shift-keying demodulators are the key components for the pulse receivers. In a pulse communication, the received signal that is generally small and the internal noise of the modulator circuit itself make the modulation difficult. To improve the input sensitivity, the symmetric amplitude-shift-keying demodulator using a dummy circuit is proposed in this paper. Measurement result using the proposed demodulator shows -33dBm input sensitivity at a data rate of 2Gbps, which is three-fold higher than those of conventional ones. This demodulator can be used for long-distance pulse communication.