A 484-µm2 21-GHz LC-VCO beneath a Stacked-Spiral Inductor

This paper proposes an ultra compact LC-VCO. Due to the speed-up of CMOS digital circuits, jitter of ring oscillators is becoming a critical problem. Even though a LC-VCO has a better phase noise, a layout size of on-chip inductor is a problem as a clock generator. Thus, the proposed LC-VCO consists of a very compact stacked-spiral inductor and active components placed beneath the inductor. The VCO is implemented by a 65-nm CMOS process, and the chip area is only 484 μm². This VCO achieves a phase noise of -89.4 dBc/Hz@1MHz, power consumption of 1.92mW, and FOMA of 206 dBc/Hz.