Hardware-efficient architecture for high throughput Turbo decoder

In this paper, a hardware-efficient and high throughput Turbo decoder architecture is proposed, which employs the look-ahead structure to speed up the decoding processing. Furthermore, the proposed architecture employs smaller hardware area than the traditional method to compute the extrinsic information. The slide window method is adopted in the proposed architecture to reduce memory requirement. The proposed architecture can achieve a higher throughput ratio with a relatively low hardware cost.