Title :
SPICE simulation methodology for system level ESD design
Author :
Lou, Lifang ; Duvvury, Charvaka ; Jahanzeb, Agha ; Park, Jae
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A SPICE simulation methodology to design an isolation impedance network against the residual pulse from IEC 61000-4-2 stress for the system level ESD protection using the TLP data of transient voltage suppressors and IC interface pins is presented. Case studies are used to demonstrate the usage of this methodology.
Keywords :
SPICE; circuit simulation; electrostatic discharge; integrated circuits; surge protection; transient analysis; IC interface pins; IEC 61000-4-2 stress; SPICE simulation methodology; TLP data; isolation impedance network design; residual pulse; system level ESD design; transient voltage suppressors; Data models; IEC; Impedance; Integrated circuit modeling; Resistors; Solid modeling; Stress;
Conference_Titel :
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location :
Reno, NV
Print_ISBN :
978-1-58537-182-2
Electronic_ISBN :
978-1-58537-182-2
