Predictive full circuit ESD simulation and analysis using extended ESD compact models: Methodology and tool implementation

Author

Li, Junjun ; Gauthier, Robert ; Joshi, Amol ; Lundberg, Martin ; Connor, John ; Chang, Shunhua ; Mitra, Souvick ; Muhammad, Mujahid

Author_Institution

Semicond. R&D Center, IBM, Essex Junction, VT, USA

fYear

2010

fDate

3-8 Oct. 2010

Firstpage

1

Lastpage

8

Abstract

We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to hardware data correlation.

Keywords

CMOS integrated circuits; circuit optimisation; circuit simulation; electrostatic discharge; failure analysis; hardware description languages; integrated circuit design; ESD design simulation; ESTEEM; Verilog-A; circuit optimization flow; extended ESD compact models; failure analysis; hardware data correlation simulation; predictive full circuit ESD simulation; Analytical models; Electrostatic discharge; Integrated circuit modeling; Inverters; Logic gates; MOS devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd

Conference_Location

Reno, NV

Print_ISBN

978-1-58537-182-2

Electronic_ISBN

978-1-58537-182-2

Type

conf

Filename

5623721