Title :
Cross domain protection analysis and verification using whole chip ESD simulation
Author :
Okushima, Mototsugu ; Kitayama, Tomohiro ; Kobayashi, Susumu ; Kato, Tetsuya ; Hirata, Morihisa
Author_Institution :
Renesas Electron. Corp., Kawasaki, Japan
Abstract :
A whole-chip simulation methodology of the full ESD paths including the full-chip power and ground wiring network has been established, and successfully demonstrated on products with several hundreds of pins. By checking voltage stress across cross domain circuits itself, marginal cross domain ESD design window in sub-100nm SoCs can be extended.
Keywords :
CMOS digital integrated circuits; circuit simulation; electrostatic discharge; system-on-chip; SoC; cross domain protection analysis; full-chip power network; ground wiring network; marginal cross domain ESD design window; voltage stress checking; whole chip ESD simulation methodology; Clamps; Electrostatic discharge; Integrated circuit modeling; Layout; Resistance; Stress; Wiring;
Conference_Titel :
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location :
Reno, NV
Print_ISBN :
978-1-58537-182-2
Electronic_ISBN :
978-1-58537-182-2
