DocumentCode
533358
Title
Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations
Author
Yang, Yang ; Gauthier, Robert ; Sarro, James Di ; Li, Junjun ; Mitra, Souvick ; Chatty, Kiran ; Mishra, Rahul ; Ioannou, Dimitris E.
Author_Institution
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
fYear
2010
fDate
3-8 Oct. 2010
Firstpage
1
Lastpage
8
Abstract
We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress in real input/output circuits. The stress on the receiver is of greater concern than is stress on the driver due to different gate oxide areas under stress. Methods to improve pad voltage tolerance for gate oxide breakdown are proposed.
Keywords
MOSFET; electric breakdown; electrostatic discharge; high-k dielectric thin films; ESD stress configurations; MOSFET gate oxide thickness; input-output circuits; pad voltage tolerance; pulsed high-k gate dielectric breakdown; receiver; size 32 nm; Clamps; Electrostatic discharge; Immune system; Logic gates; MOSFET circuits; Stress; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location
Reno, NV
Print_ISBN
978-1-58537-182-2
Electronic_ISBN
978-1-58537-182-2
Type
conf
Filename
5623726
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