• DocumentCode
    533361
  • Title

    Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies

  • Author

    Mitra, Souvick ; Gauthier, Robert ; Chang, Shunhua ; Li, Junjun ; Halbach, Ralph ; Seguin, Chris

  • Author_Institution
    Semicond. R&D Center, IBM, Essex Junction, VT, USA
  • fYear
    2010
  • fDate
    3-8 Oct. 2010
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In advanced SOI technologies, the bottom gate voltage plays an important role in achieving the maximum trigger voltage Vt1 of the cascoded drivers. A comparable MOSFET and BJT current handling is needed to ensure maximum Vt1. The minimum and maximum Vt1 window for cascoded driver is shown to range between a single FET Vt1 and twice single FET Vt1.
  • Keywords
    MOSFET; bipolar transistors; driver circuits; silicon-on-insulator; BJT current handling; ESD design window; MOSFET; SOI technology; bottom gate voltage; cascoded drivers; size 45 nm; trigger voltage; twice single FET; Driver circuits; Earth Observing System; Electrostatic discharge; FETs; Logic gates; MOSFET circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
  • Conference_Location
    Reno, NV
  • Print_ISBN
    978-1-58537-182-2
  • Electronic_ISBN
    978-1-58537-182-2
  • Type

    conf

  • Filename
    5623730
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=533361