Title :
A new ESD design methodology for high voltage DMOS applications
Author :
Malobabic, Slavica ; Salcedo, Javier A. ; Righter, Alan W. ; Hajjar, Jean-Jacques ; Liou, Juin J.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
Abstract :
A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high voltage NLDMOS functional blocks is introduced. Optimizing high voltage output stage design for robust device- and system-level (IEC 61000-4-2)/HMM is assessed under 1-, 2-, 5-, 10-, 100-ns wide time frames of typical electrostatic discharge (ESD) stress models.
Keywords :
MOS integrated circuits; electrostatic discharge; integrated circuit design; ESD design methodology; HMM; IEC 61000-4-2 system-level; electrostatic discharge stress models; high sensitive high voltage NLDMOS functional blocks; high voltage DMOS applications; high voltage output stage design optimisation; time 1 ns; time 10 ns; time 100 ns; time 2 ns; time 5 ns; Clamps; Current measurement; Electrostatic discharge; Hidden Markov models; Leakage current; Logic gates; Stress;
Conference_Titel :
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location :
Reno, NV
Print_ISBN :
978-1-58537-182-2
Electronic_ISBN :
978-1-58537-182-2
