DocumentCode
533378
Title
Solutions to mitigate parasitic NPN bipolar action in high voltage analog technologies
Author
Salman, Akram A. ; Boselli, Gianluca ; Kunz, Hans ; Brodsky, Jonathan
Author_Institution
Analog Technol. Dev. ESD Lab., Texas Instrum. Inc., Dallas, TX, USA
fYear
2010
fDate
3-8 Oct. 2010
Firstpage
1
Lastpage
8
Abstract
This is a study of the parasitic NPN premature turn-on for high voltage BiCMOS technologies. In this work, we will investigate several methods to suppress its turn-on. Using TCAD and TLP we will investigate solutions based on increased well spacing, offset of wells, self-protection and beta reduction through highly doped base implant. We will also investigate the limitations associated with each of these solutions.
Keywords
BiCMOS analogue integrated circuits; power integrated circuits; technology CAD (electronics); TCAD; TLP; beta reduction; high voltage BiCMOS technologies; high voltage analog technologies; highly doped base implant; parasitic NPN bipolar action; self-protection; BiCMOS integrated circuits; Doping; Electrostatic discharge; Junctions; Layout; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location
Reno, NV
Print_ISBN
978-1-58537-182-2
Electronic_ISBN
978-1-58537-182-2
Type
conf
Filename
5623748
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