Title :
Investigation of current flow during wafer-level CDM using real-time probing
Author :
Jack, Nathan ; Shukla, Vrashank ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.
Keywords :
circuit simulation; failure analysis; test equipment; wafer level packaging; I/O failures; circuit simulation; core failures; induced current stress; package-level FICDM testers; real-time voltage probing; wafer-level CDM test methods; Current measurement; Probes; Radio frequency; Real time systems; Semiconductor device measurement; Stress; Voltage measurement;
Conference_Titel :
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location :
Reno, NV
Print_ISBN :
978-1-58537-182-2
Electronic_ISBN :
978-1-58537-182-2
