Layout optimizations of adiabatic booth multipliers

Author

Jiang, Jintao ; Lu, Binbin ; Hu, Jianping

Author_Institution

Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China

Volume

1

fYear

2010

fDate

1-2 Aug. 2010

Firstpage

75

Lastpage

78

Abstract

This paper presents layout optimization methods for complementary pass-transistor adiabatic logic (CPAL) circuits in order to make the circuits more energy-efficient. The layout optimisations for a low-power tree multiplier based on modified Booth algorithm is carried out. The multiplier has been realized with TSMC 0.18μm CMOS process technology with full-custom layouts, and full parasitic extraction is done. Compared with its layout of counterpart in conventional logic (static complementary CMOS logic), the adiabatic multiplier attains large energy savings.

Keywords

CMOS logic circuits; circuit layout; circuit optimisation; logic circuits; multiplying circuits; trees (mathematics); CMOS process technology; CPAL circuits; TSMC; adiabatic booth multipliers; adiabatic multiplier; complementary pass-transistor adiabatic logic circuits; conventional logic; full parasitic extraction; full-custom layouts; layout optimizations; low-power tree multiplier; modified Booth algorithm; size 0.18 mum; static complementary CMOS logic; Generators; Transistors; Adiabatic multiplier; CPAL; Layout optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits,Communications and System (PACCS), 2010 Second Pacific-Asia Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-7969-6

Type

conf

DOI

10.1109/PACCS.2010.5627021

Filename

5627021