XML component-based modeling for digital circuits

This paper presents a method of scheduler modeling for components of embedded systems, making the specification and verification process practical for real designs. In this method, designers can regard all circuits as components. A bigger component is constructed from those smaller components connecting with connectors (wires). Designers specify components in XML, and simulate their behaviors and verify their correctness. All components can be mapped into Verilog or VHDL automatically. This method supports hierarchical models, provides an efficient simple solution to model and verify our design quickly, and can be used in design and verification of embedded systems.