A digital channelized receiver architecture with low calculation cost

In this paper, from the point of view reducing the system calculation cost, a digital channelized receiver is proposed. The decimation factor of the proposed digital channelized receiver with low calculation cost is equal to the number of signal channels, which is acquired by changing the input signal of the embedded instantaneous frequency measurement receiver. Due to the increase of the system decimation factor, the data to be processed are decreased and the system processing speed is improved indirectly. In this paper, the architecture and working principle of the proposed digital channelized receiver with low calculation cost is firstly given; secondly, the overlapping channel division method used in the digital channelized receiver with low calculation cost is put forward. Meanwhile, the channel arbitration method of the unmodulated or modulated signal in the case of overlapping channel division is analyzed. Then, the frequency measurement principle of the embedded instantaneous frequency measurement receiver is deduced in detail. Through the use of the overlapping channel division method, the proposed digital channelized receiver with low calculation cost is able to avoid the existence of blind spots between channels and increases the interception probabilities of the input signals. And, the proposed digital channelized receiver can distinguish two signals coming simultaneously to the same channel by using the overlapping channel division method. In addition, the channel of the input signal truly residing can be simply determined by using the channel arbitration in the case of overlapping channel division and according to the output frequency of the embedded instantaneous frequency measurement receiver. Finally, the related simulation results verify the correctness and feasibility of the theories and method involved in this paper.