Pin-shape assessment for interlayer-cooled chip stacks with periodic boundary condition modeling

Volumetric heat removal in high-performance 3D chip stacks can be performed by means of interlayer cooling. The heat is absorbed in water, which is pumped in the liquid phase into the cavities between the active layers. Individual through-silicon vias (TSV), which maintain the electrical communication between the layers, are embedded into silicon pins in the fluid cavity. Thousands of these TSVs are arranged on an equidistant grid. The mass transfer and consequently the heat removal strongly depend on the silicon pin-shape, which were assessed in this study.