DocumentCode :
53499
Title :
A Simulation Study on Process Sensitivity of a Line Tunnel Field-Effect Transistor
Author :
Walke, Amey Mahadev ; Vandenberghe, W.G. ; Kao, Kuo-Sheng ; Vandooren, A. ; Groeseneken, Guido
Author_Institution :
Imec, Leuven, Belgium
Volume :
60
Issue :
3
fYear :
2013
fDate :
Mar-13
Firstpage :
1019
Lastpage :
1027
Abstract :
A process sensitivity study of a steep subthreshold swing line tunnel field-effect transistor is presented for the first time using 2-D quantum-mechanical device simulations. The impact of various process parameters on the device transfer characteristics is presented with the help of process splits. A study of the thermal budget also shows that an increase in epitaxial growth thermal budget degrades the device performance by increasing the tunneling onset voltage VTON and the off-current. Through process simulation and Plackett-Burman design of experiment (PB-DOE), the epitaxial layer thickness of the channel was identified as the most critical parameter in device processing. A thickness variation from 2 to 3 nm in the highly ( 7 × 1019 cm-3) doped epitaxial was found to cause ~ 500-mV change in the tunneling onset voltage. It was found that an increase in doping concentration in the epitaxial layer to reduce quantum confinement effects will lead to an increase in the sensitivity of the device to the thickness of the epitaxial layer. A thicker epitaxial layer (5-6 nm) with lower doping concentration is recommended for reduced epitaxial layer variation sensitivity.
Keywords :
design of experiments; epitaxial growth; field effect transistors; semiconductor doping; semiconductor epitaxial layers; tunnel transistors; 2D quantum mechanical device simulation; PB-DOE; Plackett-Burman design of experiment; channel epitaxial layer thickness; device processing; device sensitivity; device transfer characteristics; doping concentration; epitaxial growth; epitaxial layer variation sensitivity reduction; highly-doped epitaxial; off-current; process parameters; process sensitivity; process splits; quantum confinement effect reduction; size 5 nm to 6 nm; steep subthreshold swing line tunnel field effect transistor; thermal budget; tunneling onset voltage; Doping; Epitaxial growth; Epitaxial layers; Logic gates; Semiconductor process modeling; Sensitivity; Tunneling; Plackett–Burman design of experiment (PB-DOE); TFET; process simulation of tunnel field-effect transistors (TFETs); process variation sensitivity;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2013.2242201
Filename :
6461086
Link To Document :
بازگشت