Title :
The Implementation of Block Low-Density Parity-Check Code Codec on FPGA
Author :
Xue, Wen ; Wang, Jianxin ; Liu, Guangzu ; Chen, Riqin
Author_Institution :
Sch. of Electron. & Opt. Eng., Nanjing Univ. of Sci. & Technol., Nanjing, China
Abstract :
In this paper we introduce the implementation of a block-LDPC codec on FPGA with simulation. The result shows that this codec is suitable for block LDPC with less resource consumption.
Keywords :
codecs; field programmable gate arrays; FPGA; block low density parity check code codec; block-LDPC codec; resource consumption; Bit error rate; Codecs; Decoding; Field programmable gate arrays; Parity check codes; Random access memory; Timing;
Conference_Titel :
E-Product E-Service and E-Entertainment (ICEEE), 2010 International Conference on
Conference_Location :
Henan
Print_ISBN :
978-1-4244-7159-1
DOI :
10.1109/ICEEE.2010.5661521
