DocumentCode :
540165
Title :
Video Encoder Architecture for MPEG2 Real Time Encoding
Author :
Jyh-Shin Pan ; Geng-Lin Chen ; Jia-Lung Wang
fYear :
1996
fDate :
5-7 June 1996
Firstpage :
34
Abstract :
A video encoder architecture for encoding digital video signals based on the MPEG2 video standard up to slice level is described. Function specific architecture is implemented to increase coding eficiency and reduce the silicon area for real time encoding. Hierarchical controlling concept is adopted and three stage pipeline encoding method is used in macroblock coding to increase the flexibility of encoding flow and reduce the design effort.
Keywords :
Computer architecture; Encoding; Motion estimation; Pipelines; Real-time systems; Streaming media; Transform coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics, 1996. Digest of Technical Papers., International Conference on
Print_ISBN :
0-7803-3029-3
Type :
conf
DOI :
10.1109/ICCE.1996.517198
Filename :
5726329
Link To Document :
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