Design considerations for 60 GHz CMOS power amplifiers

This paper describes design considerations for millimeter-wave CMOS power amplifiers (PA). Solutions are presented from device level to circuit level and demonstrated by a measured 60 GHz PA prototype in 65 nm bulk CMOS technology. The proposed PA achieves a peak output power of 14 dBm with a peak power-added efficiency (PAE) of 7.2%. The small signal gain is 10.2 dB and 1-dB compression output power is 10.8 dBm. The transformer-based passives employed in the design enable a compact layout with an active area of 0.3 mm². The PA consumes a quiescent current of 143 mA from a 1.6 V supply voltage.