Title :
A 57–66 GHz medium power amplifier in 65-nm CMOS technology
Author :
Hsieh, Chia-Yu ; Kuo, Jhe-Jia ; Tsai, Zuo-Min ; Lin, Kun-You
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents the design and measurement results of a 57-66 GHz medium power amplifier in 65-nm LP CMOS process. This amplifier is designed with broadband matching concern, which can achieve a measured gain more than 21 dB from 57-66 GHz and have a 3-dB bandwidth more than 14 GHz while consuming 54 mW from a 1.2 V supply. The measured results exhibit Psat of 10.3 dBm, P1dB of 6.2 dBm, and the peak PAE is 16 %at 58 GHz. The chip size is only 0.3 mm2.
Keywords :
CMOS integrated circuits; power amplifiers; CMOS technology; LP CMOS process; frequency 57 GHz to 66 GHz; medium power amplifier; power 54 mW; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Impedance matching; Loss measurement; MOS devices; Radio frequency; Topology; 60 GHz; Broadband; CMOS; MMIC; power amplifiers;
Conference_Titel :
Microwave Conference Proceedings (APMC), 2010 Asia-Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-7590-2
Electronic_ISBN :
978-1-902339-22-2
