Large signal model and CAD implementation of impact ionization for FET devices

This paper presents a large signal model of impact ionization effects of FETs and its CAD implementation. The model is compact, describes the effects observed in the gate and drains current in a simple way, converges well in harmonic balance simulation. The model is verified for various FET devices and materials like GaAs SiC, GaN, and InSb. By using this model, the prediction accuracy for P_out and PAE is improved, especially when the device is pushed to the limits and impact ionization can be observed. When aware for the problem, the designer is able to construct in a better way the input and output matching circuits to avoid operating the device in the dangerous regions of operation and hence improve reliability.