High-frequency half-integral subharmonic locked ring-VCO-based scalable PLL in 90 nm CMOS

A wide-frequency-range ring-VCO-based PLL with half-integral subharmonic locking was realized (PLL area: 0.11mm²) by adopting 90nm CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL (frequency tuning range: 1.2-2.4 GHz) that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL (frequency tuning range: 6.1-10.4 GHz) that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 46MHz input reference signal, the 1-MHz-offset phase noise of the PLL was -89 dBc/Hz without injection locking (PLL output frequency: 6.62 GHz = 4.5 × 32 × 46 MHz); with half-integral subharmonic locking at the same output frequency, the 1-MHz-offset phase noise was -99 dBc/Hz (power consumption from a 1.0V power supply: 23 mW).