Versatile Compact Model for Graphene FET Targeting Reliability-Aware Circuit Design

In this paper, we report on the development of a versatile compact model for graphene FETs (GFETs). Aging studies have been performed on the GFETs via bias stress measurements and aging laws were implemented in the compact model, including failure mechanisms in the GFETs. The failure mechanisms are identified to be originated from the generation of traps and interface states causing a shift in the transfer characteristics and mobility degradation, respectively. For the development of the aging compact model, the trap density is implemented in the prestress compact model to modulate the channel potential. Moreover, the interface state generation is implemented to reflect on the modification of the source/drain access region charges. The implemented aging model is compared with reported bias-stress measurement results as well as the aging measurements carried out on chemical vapor deposition GFETs which show a very good agreement.