Title :
Design of low power high linearity front-end circuit with a novel LNA architecture
Author :
Wu, Chang-Hsi ; Lin, Yu-Po
Author_Institution :
Dept. of Electron. Eng., Lunghwa Univ. of Sci. & Technol., Taoyuan, Taiwan
Abstract :
A low-power high-linearity front-end circuit with a novel low-noise amplifier (LNA) architecture based on CMOS 0.18μm process is presented in this paper. The conversion gain of the proposed front-end circuit is mainly boosted by current-enhanced technique and current-bleeding technique. To improve the linearity and noise, a complementary common-gate LNA is employed. The proposed front-end circuit achieves measured conversion gain of 18.4dB and input third-order intercept point (IIP3) of -6 dBm under consuming power of 9.4 mW from 1.8V supply voltage. The noise figure is 8.4 dB at 100 MHz IF frequency. The size of the chip is 0.767mm × 0.96mm.
Keywords :
CMOS integrated circuits; integrated circuit design; low noise amplifiers; low-power electronics; CMOS process; LNA architecture; complementary common-gate LNA; conversion gain; current-bleeding technique; current-enhanced technique; frequency 100 MHz; gain 18.4 dB; input third-order intercept point; low power high linearity front-end circuit; low-noise amplifier architecture; noise figure 8.4 dB; power 9.4 mW; size 0.18 mum; size 0.767 mm; size 0.96 mm; voltage 1.8 V; CMOS integrated circuits; Gain; Linearity; Mixers; Noise figure; Power measurement; Radio frequency; Current-bleeding; LNA; Mixer; current-enhanced;
Conference_Titel :
Microwave Conference Proceedings (APMC), 2010 Asia-Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-7590-2
Electronic_ISBN :
978-1-902339-22-2
