Using inverter structure for 2∼6GHz low power high gain low noise amplifier

Author

Hsu, Meng-Ting ; Liu, Ta-Cheng

Author_Institution

Dept. & Inst. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Douliu, Taiwan

fYear

2010

fDate

7-10 Dec. 2010

Firstpage

346

Lastpage

349

Abstract

This paper presents a resistive-feedback amplifier and resistive-feedback inverter. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of resistive-feedback inverter for input matching. This UWB LNA is implemented by TSMC 0.18μm CMOS technology. The minimum noise figure is 3.67 dB. The amplifier provides maximum gain (S21) of 18.5 dB while drawing 10.3 mW from 1.5-V supply. This chip area is 1.028 × 0.921 mm².

Keywords

CMOS analogue integrated circuits; invertors; low noise amplifiers; low-power electronics; microwave amplifiers; ultra wideband technology; CMOS technology; TSMC; UWB LNA; current-reused technique; frequency 2 GHz to 6 GHz; gain 18.5 dB; gain 3.67 dB; low power high gain low noise amplifier; noise figure; power 10.3 mW; resistive-feedback amplifier; resistive-feedback inverter; size 0.18 mum; splitting-load inductive peaking technique; voltage 1.5 V; CMOS integrated circuits; CMOS technology; Gain; Inverters; Loss measurement; Wideband; low noise amplifier (LNA); low power; resistive-feedback inverter;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2010 Asia-Pacific

Conference_Location

Yokohama

Print_ISBN

978-1-4244-7590-2

Electronic_ISBN

978-1-902339-22-2

Type

conf

Filename

5728715