A new CMOS wideband PLL-based frequency synthesizer

A new architecture for integrated wideband PLL (phase locked loop) based frequency synthesizer is presented. The largest achieved tuning range is depended on the largest available power supply in a system. A method of multiple power supplies has been used to produce the large tuning range with a low VCO (voltage controlled oscillator) gain, which can reduce the level of reference spurs. A prototype, which is the integer-N PLL-based frequency synthesizer, is designed and fabricated in TSMC 0.18μm CMOS 1p6m+ process. Measurements show that the tuning range at center frequency 800MHz is more than 80MHz when the available largest power supply is 3V, and the phase noise performance is -100dBc/Hz at 1MHz offset from carrier and the frequency spurs is -110dBc/Hz with 4MHz reference frequency. The presented circuit consumes 50mW and occupies a die area of 1mm².