Elimination of analog switches in low-bit successive approximation ADCs

In this paper a 100 MS/s 4b ADC is simulated in a 0.18 m digital CMOS process by time-interleaving two SAR ADCs with 200 MHz internal clock frequency that converts 4 bits in 2 cycles. In our design, the SAR logic and DAC switches are combined with each other. This technique is helpful for reducing the complexity of the SAR ADC in low-bit applications. In these applications, we can replace the analog switches with inherent digital switches of SAR logics.